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1. An asynchronous input overriding the synchronous operation is in effect.
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When I looked in the RTL Viewer at the attached state of the design (with the unneeded signal removed from the sensitivity lists), I didn't see any asynchronous control signal used by the output register, and the register was driving the output pin directly with no logic between the pin and the register. This is why I think there is no glitching, only a synchronous change in the register output at each clock edge. The simulation waveform timescale was zoomed out too far to say there was glitching.
Honored Contributor
