Some glitches in the simualtion waveforms

If the output signals are assigned inside the edge sensitive process, in other words, the signals are connected to FlipFlop outputs in your design, glitches can only occur in two cases, I think:

1. An asynchronous input overriding the synchronous operation is in effect.

2. An input signal is violating setup or hold timing requirement. In this case, your stimulating waveform would be the reason. if a similar situation is also expected in real operation, the respective signals should be synchronized to the clock before entering the logic.

You're able to recognize the reason in your simulation. If it's not obvious from a the displayed signals, you can add internal signals as outputs to the simulation. As already said, timing violation are also reported during simulation and can be traced in detail.