bhunt
New Contributor
2 years agoSimulation problem with Avalon-MM clock crossing bridge
Hi there,
I'm using the avalon MM clock-crossing bridge with questasim. After generating the core in Quartus Prime, I compile it in questasim with no issues. However, in simulation, all of its output ports are stuck at X.
I found that the IP simulation model outputs X normally, after reset, until the first transaction is passed through it. Then the IP outputs stay non-X.