Simulation Problem Multiplier 8 bits

Here is the code:

Library ieee;

use ieee.std_logic_1164.all;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

entity Multiplier8 is port (clk : in std_logic;

done : out std_logic ;

reset : in std_logic ;

Multiplier : in std_logic_vector(7 downto 0);

Multiplicand : in std_logic_vector(7 downto 0);

Product : out std_logic_vector(15 downto 0);

start : in std_logic ) ;

end Multiplier8;

architecture behavior of Multiplier8 is

type state_type is (s0, s1, s2);

signal state : state_type ;

signal A,B,Q : std_logic_vector (7 downto 0);

signal ab : std_logic_vector (8 downto 0);

signal p : std_logic_vector (3 downto 0);

signal Product1,Product2 : std_logic_vector (16 downto 0);

begin

process(clk,reset)

begin

if reset='1' then state<=s0;

elsif clk'event and clk='1' then

case state is

when s0=> if start='1' then state<=s1; p<="1000"; else state<=s0; end if;

when s1=> p<=p-1; state<=s2;

when s2=> if p="0000" then state<=s0; done<='1'; else state<=s1; end if;

end case;

end if;

end process;

process(state)

begin

case state is

when s0=> A<="00000000"; Q<=Multiplier; B<=Multiplicand;

when s1=> if Q(0)='1' then ab<=('0' & A) + ('0' & B ); end if;

when s2=> Product1<= (ab & Q); Product2<= '0' & Product1(16 downto 1); Product<=Product2(15 downto 0);

end case;

end process;

end behavior;

But when i start the simulation the are nodes problems. The program is for a 8 bit Multiplier with shift.