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Honored Contributor
Honored ContributorSimulation Problem Multiplier 8 bits
Here is the code: Library ieee; use ieee.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity Multiplier8 is port (clk : in std_logic; ...
Altera_ForumHonored Contributor
Honored ContributorApart from known weaknesses of Max plus II VHDL handling, it's complaints about the shown code seem reasonable.
It's storing several intermediate results in combinational latches. It's questionable if they will consistent.