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Altera_Forum
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14 years ago

Simulation Problem Multiplier 8 bits

Here is the code: Library ieee; use ieee.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity Multiplier8 is port (clk : in std_logic; ...
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Altera_Forum
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14 years ago

The problem is the latches in the 2nd process. To prevent latch creation in an asynchronous process, every output needs to be assigned in EVERY branch. You are also missing signals from the sensitivity list.