Hi, good afternoon, I am doing an FPGA project in which I use two components from the Quartus Prime 18.0 library: PLL intel fpga ip and the PLL Reconfig intel fpga ip. With these two components I am able to change the relog output through a selection signal. I wanted to know if anyone in the forum knows how the project simulation should be, since having so many signals I get lost in the simulation. Thanks in advance.

Unfortunately, I currently did not have the design example for the lite version. I really apologies.

simulation of pll intel fpga ip with pll reconfig intel fpga ip

AqidAyman_Altera
Regular Contributor
2 years ago
I afraid that I am not much understand what you mean by how the simulation should be done. Can you elaborate more on that?
Do you mean which signals need to be included in the simulation?
- Elias97
  New Contributor
  2 years ago
  Hello, thanks for the answer, of course that and also what signal configuration would I have to have to obtain the output of the relog.
AqidAyman_Altera
Regular Contributor
2 years ago
Maybe you can start from generating the functional simulation model when you generate the IP core. You can refer below link on how to generate the simulation files from the Intel IP Core.
https://www.intel.com/content/www/us/en/docs/programmable/683102/23-1/generating-ip-simulation-files.html

Alternatively, I also recommend you to this example design below for the simulation. This design example consists of the IOPLL IP core, and IOPLL Reconfig IP core:
https://www.intel.com/content/www/us/en/design-example/763982/intel-agilex-7-fpga-i-o-pll-reconfiguration.html?wapkw=PLL%20Reconfig%20intel%20fpga%20ip
Elias97
New Contributor
2 years ago
Thanks for the answer, I can't see the example because I have the Quartus Prime Lite 18.0 version, do you have another example for my version?
AqidAyman_Altera
Regular Contributor
2 years ago
Unfortunately, I currently did not have the design example for the lite version. I really apologies.