Forum Discussion
Elias97
New Contributor
New Contributorsimulation of pll intel fpga ip with pll reconfig intel fpga ip
Hi, good afternoon, I am doing an FPGA project in which I use two components from the Quartus Prime 18.0 library: PLL intel fpga ip and the PLL Reconfig intel fpga ip. With these two components I am ...
Unfortunately, I currently did not have the design example for the lite version. I really apologies.
AqidAyman_Altera
Regular Contributor
Regular ContributorI afraid that I am not much understand what you mean by how the simulation should be done. Can you elaborate more on that?
Do you mean which signals need to be included in the simulation?
Elias97Hello, thanks for the answer, of course that and also what signal configuration would I have to have to obtain the output of the relog.
