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Elias97's avatar
Elias97
Icon for New Contributor rankNew Contributor
2 years ago
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simulation of pll intel fpga ip with pll reconfig intel fpga ip

Hi, good afternoon, I am doing an FPGA project in which I use two components from the Quartus Prime 18.0 library: PLL intel fpga ip and the PLL Reconfig intel fpga ip. With these two components I am ...
  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    2 years ago

    Unfortunately, I currently did not have the design example for the lite version. I really apologies.


AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Maybe you can start from generating the functional simulation model when you generate the IP core. You can refer below link on how to generate the simulation files from the Intel IP Core.

https://www.intel.com/content/www/us/en/docs/programmable/683102/23-1/generating-ip-simulation-files.html


Alternatively, I also recommend you to this example design below for the simulation. This design example consists of the IOPLL IP core, and IOPLL Reconfig IP core:

https://www.intel.com/content/www/us/en/design-example/763982/intel-agilex-7-fpga-i-o-pll-reconfiguration.html?wapkw=PLL%20Reconfig%20intel%20fpga%20ip