Forum Discussion
Elias97
New Contributor
New Contributorsimulation of pll intel fpga ip with pll reconfig intel fpga ip
Hi, good afternoon, I am doing an FPGA project in which I use two components from the Quartus Prime 18.0 library: PLL intel fpga ip and the PLL Reconfig intel fpga ip. With these two components I am ...
Unfortunately, I currently did not have the design example for the lite version. I really apologies.
AqidAyman_Altera
Regular Contributor
Regular ContributorMaybe you can start from generating the functional simulation model when you generate the IP core. You can refer below link on how to generate the simulation files from the Intel IP Core.
Alternatively, I also recommend you to this example design below for the simulation. This design example consists of the IOPLL IP core, and IOPLL Reconfig IP core:
