Silicon Speed

Temperature increases with increasing switching frequency (the faster you run it the hotter it gets). This is because the transistors spend more "average time" in the switching state (neither on nor off) which is when they really draw current.

Maximum switching frequency decreases with increasing temperature (the hotter you run it the slower you have to run it). This is due to physical effects of temperature on the silicon (electron mobility primarily, switching thresholds, etc). Everything just takes longer to move around when things get hot. So it takes longer for those transistors to change state and it takes longer for charge to travel between transistors.

Decreasing the temperature has the opposite effect. As you decrease (or maintain) the temperature, you create an environment where higher switching frequencies can take place (or be maintained). So if you want to increase your maximum switching frequency, you have to lower the temperature. And of course if things get too hot the physical components of the IC can breakdown causing permanent damage. (I've seen CPU's explode when cooling was removed too rapidly).

This is why you will see hard core PC gamers apply extreme cooling solutions to their processors so that they can achieve extreme overclocking.

Does this help?

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I always believed that silicon is faster at lower temperatures and slower at hotter temperatures, but that the core current in an FPGA is lower at a lower temperature than a higher temperature. Am I correct in saying this?

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In General, yes: The transistors are capable of switching faster at lower temperatures, of course there are circuits that can slow the transistors down at low temp, but these are usually reserved for IO's and timing sensitive circuits where they would prefer a constant speed over temp. (IE in IO's to reduce excessive ringing at cold temps, and in oscillators, etc.) Of course the world isn't perfect, so the best they can usually do is have it run fastest at room temp, and slow down evenly at hot/cold. (make it a U shape instead of a ramp profile)

The power is make of of two parts, the static, power which is dominated by the leakage current of the transistors and the dynamic power which is dominated by the capacitance, frequency, and voltage of operation (CV^2F). Since the design must operate over temperature, the Frequency of the design is set based on it's slowest operating point (Hot), so it is usually constant, so the power change is dominated by leakage changes.

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Also I thought that the higher current is due to leakage which in turn is due to the fact that in a faster device, the transistors are almost 'turned on'.

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Yes the higher current is due to leakage, though the "Off" transistors, this is an effect of the transistor geometry and temperature, the geometry of today's "Faster" transistors are smaller and have more leakage current, even though they may not be switching at all. This problem gets worse at higher temperatures.

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This is where I get confused, because going by what I wrote above, a device operating at a low temperature should run faster and draw less current, but if it runs faster, there would also be more leakage thus increasing the current. Whereas a device running at a hotter temp would run slower but draw less current, when it should draw more.

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Ok, where are are getting confused is you are equating leakage with speed, when in reality leakage is based on geometry of the transistor, and is a static effect, in any particular device it's driven by temperature.

Dynamic power is driven by CV^2F, but the F term frequency is set by the fastest speed the device can run at at any temperature, so usually all of these are constant across temperature.

Now on the risk of confusing you more, instantaneous power due to faster edge rates and thus faster F in the above power equation actually does go up at lower temperature, but this is still averaged over the same cycle period. (IE if it takes 10 ns from one register to another at hot, the power switching power is spread out over the 10 ns as it goes though each stage of logic. At cold it might only take 5 ns to get though the logic, so the same amount of power is not compressed in the first 5 ns of the 10 ns period but the average of the two is the same.

Now yes, theoretically you could run the design at 200 MHz -vs- 100 MHz in the above case at cold, but then it would function as the design warmed, up.

Now just to though another wrench into the game, there's also another player called switch-though current. This occurs due to the fact that there are really two transistors in CMOS logic design (P and N transistors). One is connected to the VCC rail, on one end and the other connected to ground. They turn on at opposite voltages, but are both partially on in the as the control signal is going from one state to the next.

Since the transistors driving the control for the next stage are slowing down at hot, this causes the next stage to be in the "transitional" state where both transistors are partially

on for a longer period of time causing more switch though power at hot as well.

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I would like if someone could straighten this one out for me and explain what exactly increases/decreases the current/speed at high and low temperatures as I clearly don't have the full picture.

Many thanks for your help

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Hopefully I got it all..

anakha and jakobjones, many thanks for the responses. I have things much clearer in my head now.

I just have 2 other related queries on this subject of silicon speed which I hadn´t thought of when i initially posted the question:

When I use quartus to place a timing constraint for example the tpd through some logic. If I specify to quartus that the operating temperature range is between -40 deg and 100 deg, how does quartus garuntee that this time will be the same at -40 and 100. For example if I have a device in the desert where there are huge swings in the temperature between night and day, how is this implemented on the FPGA to ensure that the timing doesn´t cause any problems when the temperature swings so much?

Also some time ago, I read that on stratix III and IV devices (if I remember correctly) that they can operate slower at cold temp and faster at hot temp. I can´t recall exactly where I read this, but I remember at the time googling the term quoted for this, but couldn´t find an explantion? Does anybody know why this is? or why it occurs? or what would be the benifits for altera to do this?

Many thanks,

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When I use quartus to place a timing constraint for example the tpd through some logic. If I specify to quartus that the operating temperature range is between -40 deg and 100 deg, how does quartus garuntee that this time will be the same at -40 and 100. For example if I have a device in the desert where there are huge swings in the temperature between night and day, how is this implemented on the FPGA to ensure that the timing doesn´t cause any problems when the temperature swings so much?

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All the logic elements and routing though the FPGA are characterized across temperature and voltage, and minimum, typical and maximum corners.. Usually minimum delay (Fast corner), is low temp, high voltage, and the maxmimum (slow corner) is high temp, low voltage, and typical is type voltage, room temp.

For TPD there is usually a maximum/minimum spec. At the slow corner, it's usually the maximum settings that are violated, (Setup to the next register), the synthesis engine attempts to optimize logic, and routing to fix these. At the fast timing corner, sometimes the logic is so fast, that the clock skew is greater than the logic delay between registers, so this shows up as a hold violation. The timing engine is tries to fix these by adding additional logic or delays to meet timing.

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Also some time ago, I read that on stratix III and IV devices (if I remember correctly) that they can operate slower at cold temp and faster at hot temp. I can´t recall exactly where I read this, but I remember at the time googling the term quoted for this, but couldn´t find an explantion? Does anybody know why this is? or why it occurs? or what would be the benifits for altera to do this?

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I'm not aware of this for the Stratix III/ IV families, but what it might have pertaining to is temperature compensated delay elements. (I'm not sure if these families have these or not)

This makes it easier to fix hold violations, because the delay elements end up have the U shaped profile I mentioned before, making it so you have to add less to fix hold violations at cold, and end up having less total delay at hot. IE if it use to take 3 delay elements to fix an issue at cold, without temp compensation, it might only take one to fix it with temp compensation. So at the hot corner, you are adding only 1/3 the amount of delay that use to be there.

Anakha

Thanks again anakha

I think I have things clear now, but just one more thing..

I was reading in a handbook a while back that in the classic timing analyzer, if I place a maximum or minimum delay constraint for an output pin, but only specify one, then quartus will attempt to match this exact time.

For example if I place a constraint of maximum delay 2 ns (without specifying a minimum delay), I understand that quartus will attempt to assign the ouput in 2 ns exactly. But if the temperture swings then this may not be possible?

So does quartus attempt to assign the output in 2 ns for typical corner only meaning that at the fast and slow corners the designer would have to expect a slight error?

Would it always be advisable to specify a maximum and minumum delay in this situation, to ensure than the contraint can be meet at all corners?

Thanks again.

Hi Ardni:

Yes, if you only give a single constraint, for Maximum/Minimum, Quartus will attempt to meet that constraint under both conditions, however it will be impossible, so you'll end up with timing violations. It's always advisable to specify realistic max and min delays in that situation, so the tool can work on the real issues, instead of spinning it's wheels on a problem it can not solve.

Anakha

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I was reading in a handbook a while back that in the classic timing analyzer, if I place a maximum or minimum delay constraint for an output pin, but only specify one, then quartus will attempt to match this exact time.

...

Would it always be advisable to specify a maximum and minumum delay in this situation, to ensure than the contraint can be meet at all corners?

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Expanding on the previous reply...

Even if the timing analyzer automatically assumes a minimum constraint with the same value as the user-specified maximum or vice versa, that does not mean this is a proper way to constrain the design. As has been said, each delay in the device has a range of value over process/voltage/temperature. Constraining maximum and minimum with the same value creates unrealistic constraints that cannot be satisfied by the silicon.

The user should explicitly specify both the minimum and the maximum basing each on the actual design requirements. Your final constraints should not be artificial numbers just to come up with requirements Quartus can meet. (When you have not yet determined the real design requirements for something, you might want temporarily to use artificial requirements that produce positive slack so that the Fitter will focus its effort on other things that already have the real requirements.) A reasonable design allows a range between minimum and maximum; your constraints should reflect that same range. Hopefully the constraints that your design really needs are constraints that can actually be satisfied by the silicon in combination with the optimizations that Quartus can do in synthesis and in the Fitter.