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I was reading in a handbook a while back that in the classic timing analyzer, if I place a maximum or minimum delay constraint for an output pin, but only specify one, then quartus will attempt to match this exact time.
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Would it always be advisable to specify a maximum and minumum delay in this situation, to ensure than the contraint can be meet at all corners?
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Expanding on the previous reply...
Even if the timing analyzer automatically assumes a minimum constraint with the same value as the user-specified maximum or vice versa, that does not mean this is a proper way to constrain the design. As has been said, each delay in the device has a range of value over process/voltage/temperature. Constraining maximum and minimum with the same value creates unrealistic constraints that cannot be satisfied by the silicon.
The user should explicitly specify both the minimum and the maximum basing each on the actual design requirements. Your final constraints should not be artificial numbers just to come up with requirements Quartus can meet. (When you have not yet determined the real design requirements for something, you might want temporarily to use artificial requirements that produce positive slack so that the Fitter will focus its effort on other things that already have the real requirements.) A reasonable design allows a range between minimum and maximum; your constraints should reflect that same range. Hopefully the constraints that your design really needs are constraints that can actually be satisfied by the silicon in combination with the optimizations that Quartus can do in synthesis and in the Fitter.
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