Silicon Speed

anakha and jakobjones, many thanks for the responses. I have things much clearer in my head now.

I just have 2 other related queries on this subject of silicon speed which I hadn´t thought of when i initially posted the question:

When I use quartus to place a timing constraint for example the tpd through some logic. If I specify to quartus that the operating temperature range is between -40 deg and 100 deg, how does quartus garuntee that this time will be the same at -40 and 100. For example if I have a device in the desert where there are huge swings in the temperature between night and day, how is this implemented on the FPGA to ensure that the timing doesn´t cause any problems when the temperature swings so much?

Also some time ago, I read that on stratix III and IV devices (if I remember correctly) that they can operate slower at cold temp and faster at hot temp. I can´t recall exactly where I read this, but I remember at the time googling the term quoted for this, but couldn´t find an explantion? Does anybody know why this is? or why it occurs? or what would be the benifits for altera to do this?

Many thanks,