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When I use quartus to place a timing constraint for example the tpd through some logic. If I specify to quartus that the operating temperature range is between -40 deg and 100 deg, how does quartus garuntee that this time will be the same at -40 and 100. For example if I have a device in the desert where there are huge swings in the temperature between night and day, how is this implemented on the FPGA to ensure that the timing doesn´t cause any problems when the temperature swings so much?
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All the logic elements and routing though the FPGA are characterized across temperature and voltage, and minimum, typical and maximum corners.. Usually minimum delay (Fast corner), is low temp, high voltage, and the maxmimum (slow corner) is high temp, low voltage, and typical is type voltage, room temp.
For TPD there is usually a maximum/minimum spec. At the slow corner, it's usually the maximum settings that are violated, (Setup to the next register), the synthesis engine attempts to optimize logic, and routing to fix these. At the fast timing corner, sometimes the logic is so fast, that the clock skew is greater than the logic delay between registers, so this shows up as a hold violation. The timing engine is tries to fix these by adding additional logic or delays to meet timing.
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Also some time ago, I read that on stratix III and IV devices (if I remember correctly) that they can operate slower at cold temp and faster at hot temp. I can´t recall exactly where I read this, but I remember at the time googling the term quoted for this, but couldn´t find an explantion? Does anybody know why this is? or why it occurs? or what would be the benifits for altera to do this?
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I'm not aware of this for the Stratix III/ IV families, but what it might have pertaining to is temperature compensated delay elements. (I'm not sure if these families have these or not)
This makes it easier to fix hold violations, because the delay elements end up have the U shaped profile I mentioned before, making it so you have to add less to fix hold violations at cold, and end up having less total delay at hot. IE if it use to take 3 delay elements to fix an issue at cold, without temp compensation, it might only take one to fix it with temp compensation. So at the hot corner, you are adding only 1/3 the amount of delay that use to be there.
Anakha
Honored Contributor
