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I always believed that silicon is faster at lower temperatures and slower at hotter temperatures, but that the core current in an FPGA is lower at a lower temperature than a higher temperature. Am I correct in saying this?
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In General, yes: The transistors are capable of switching faster at lower temperatures, of course there are circuits that can slow the transistors down at low temp, but these are usually reserved for IO's and timing sensitive circuits where they would prefer a constant speed over temp. (IE in IO's to reduce excessive ringing at cold temps, and in oscillators, etc.) Of course the world isn't perfect, so the best they can usually do is have it run fastest at room temp, and slow down evenly at hot/cold. (make it a U shape instead of a ramp profile)
The power is make of of two parts, the static, power which is dominated by the leakage current of the transistors and the dynamic power which is dominated by the capacitance, frequency, and voltage of operation (CV^2F). Since the design must operate over temperature, the Frequency of the design is set based on it's slowest operating point (Hot), so it is usually constant, so the power change is dominated by leakage changes.
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Also I thought that the higher current is due to leakage which in turn is due to the fact that in a faster device, the transistors are almost 'turned on'.
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Yes the higher current is due to leakage, though the "Off" transistors, this is an effect of the transistor geometry and temperature, the geometry of today's "Faster" transistors are smaller and have more leakage current, even though they may not be switching at all. This problem gets worse at higher temperatures.
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This is where I get confused, because going by what I wrote above, a device operating at a low temperature should run faster and draw less current, but if it runs faster, there would also be more leakage thus increasing the current. Whereas a device running at a hotter temp would run slower but draw less current, when it should draw more.
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Ok, where are are getting confused is you are equating leakage with speed, when in reality leakage is based on geometry of the transistor, and is a static effect, in any particular device it's driven by temperature.
Dynamic power is driven by CV^2F, but the F term frequency is set by the fastest speed the device can run at at any temperature, so usually all of these are constant across temperature.
Now on the risk of confusing you more, instantaneous power due to faster edge rates and thus faster F in the above power equation actually does go up at lower temperature, but this is still averaged over the same cycle period. (IE if it takes 10 ns from one register to another at hot, the power switching power is spread out over the 10 ns as it goes though each stage of logic. At cold it might only take 5 ns to get though the logic, so the same amount of power is not compressed in the first 5 ns of the 10 ns period but the average of the two is the same.
Now yes, theoretically you could run the design at 200 MHz -vs- 100 MHz in the above case at cold, but then it would function as the design warmed, up.
Now just to though another wrench into the game, there's also another player called switch-though current. This occurs due to the fact that there are really two transistors in CMOS logic design (P and N transistors). One is connected to the VCC rail, on one end and the other connected to ground. They turn on at opposite voltages, but are both partially on in the as the control signal is going from one state to the next.
Since the transistors driving the control for the next stage are slowing down at hot, this causes the next stage to be in the "transitional" state where both transistors are partially
on for a longer period of time causing more switch though power at hot as well.
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I would like if someone could straighten this one out for me and explain what exactly increases/decreases the current/speed at high and low temperatures as I clearly don't have the full picture.
Many thanks for your help
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Hopefully I got it all..
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