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Altera_Forum's avatar
Altera_Forum
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13 years ago

signal tap killing clocks..

Ok, I don't understand how this could happen, but its happening..

I have a simple design, at the heart is a basic clock divider of a 50mhz clock, making 20 clocks..

without signal tap enabled, I can put my logic probe on the clock pins & see that they are there, & they are oscillating.

I add signal tap data, using one of my derived clocks as the signal tap clock. recomple reprogram, put my probe on a clock pin, its gone, stays logic 0. I go into signal tap I get "waiting for clock".

I remove all signal tap data, recompile, reprogram, & viola the clocks are back.

Is this possible? signal tap seems to be corrupting my design... its such a valuable debugging tool, I need to have it working.. Anyone have any suggestions, or have seen anything like this before?

Thanks in advance..:confused:

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Presuming your report is correct, the conclusion is simple: Although working, the original design already involves a problem.

    Did you perform a timing analysis?
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    FVM, no I have not performed a timing analysis, as the design is still in a very basic state, & the report tells me that the slowest path in the chip is 16ns, & the fastest clock I am using is 20ns. But could you tell me your hunch of what you think is wrong?

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    The hunch is - you are creating logic clocks. These are prone to all sorts of problems.

    Either use PLL for fast clocks. Or generate clock enables to replace the slower ones.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Hmm, ok I see what you are saying, the clocks that I have generated through my clock divider circuitry are logic clocks, rather than something being fanned out of a clock generator.

    The thing is, I practice single clock synchronous design. I only use one clock in the entire chip, to avoid the issues of using multiple clocks.

    The way i use the derived clocks, is I use edge detection circuitry to identify edges in the clocks, & then I use this detected edge as the enable for the system clock, so the clock to the flip flop is the system clock, the enable gets the signal from the edge detector circuit.

    But yeah, I am using a "logic clock" to clock the signal tap circuitry, but that is the only place I use it as a clock.

    I have done post place and route simulation on loads where my clocks don't show up, & the simulation (of course) shows everything is the way it should be.

    I have even done dummy OUTPUTPORT <= '1', & monitor this signal to ensure that its not a chip programming problem, & that signal does indeed get driven high, always. So I don't thing that is the problem.

    I'm not sure whats going on, but I don't think my original conclusion is correct that signal tap interface is killing it, because I have done the exact same thing in signal tap, & all the clocks toggle, but then I touch a bit in my code or something, & the next chip load fails, with the "Waiting for clock", as well as all the clocks being stuck at '0'. It seems to be a (yay) intermittent error.

    If anybody has any suggestions, I'd be thrilled, thanks.