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Altera_Forum
Honored Contributor
Honored Contributorsignal tap killing clocks..
Ok, I don't understand how this could happen, but its happening.. I have a simple design, at the heart is a basic clock divider of a 50mhz clock, making 20 clocks.. without signal tap enab...
Altera_ForumHonored Contributor
Honored ContributorFVM, no I have not performed a timing analysis, as the design is still in a very basic state, & the report tells me that the slowest path in the chip is 16ns, & the fastest clock I am using is 20ns. But could you tell me your hunch of what you think is wrong?
