signal tap killing clocks..

Hmm, ok I see what you are saying, the clocks that I have generated through my clock divider circuitry are logic clocks, rather than something being fanned out of a clock generator.

The thing is, I practice single clock synchronous design. I only use one clock in the entire chip, to avoid the issues of using multiple clocks.

The way i use the derived clocks, is I use edge detection circuitry to identify edges in the clocks, & then I use this detected edge as the enable for the system clock, so the clock to the flip flop is the system clock, the enable gets the signal from the edge detector circuit.

But yeah, I am using a "logic clock" to clock the signal tap circuitry, but that is the only place I use it as a clock.

I have done post place and route simulation on loads where my clocks don't show up, & the simulation (of course) shows everything is the way it should be.

I have even done dummy OUTPUTPORT <= '1', & monitor this signal to ensure that its not a chip programming problem, & that signal does indeed get driven high, always. So I don't thing that is the problem.

I'm not sure whats going on, but I don't think my original conclusion is correct that signal tap interface is killing it, because I have done the exact same thing in signal tap, & all the clocks toggle, but then I touch a bit in my code or something, & the next chip load fails, with the "Waiting for clock", as well as all the clocks being stuck at '0'. It seems to be a (yay) intermittent error.

If anybody has any suggestions, I'd be thrilled, thanks.