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Altera_Forum
Honored Contributor
Honored Contributorsignal tap killing clocks..
Ok, I don't understand how this could happen, but its happening.. I have a simple design, at the heart is a basic clock divider of a 50mhz clock, making 20 clocks.. without signal tap enab...
Altera_ForumHonored Contributor
Honored ContributorThe hunch is - you are creating logic clocks. These are prone to all sorts of problems.
Either use PLL for fast clocks. Or generate clock enables to replace the slower ones.
