Self reset to FPGA

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I'm using the method in a number of production designs where the hardware guys didn't provide a hardware reset signal.

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Sorry to hear you have some hardware guys around you who are really hard and unhelpful.

I myself have used internal reset instead of external one and it worked most but not every time. We assumed if the design didn't start well then the customer will instinctively power up again or give it a shake.

The power up reset was even regular reset whenever certain errors flagged that will force the counter back to zero. This also prevented compiler from optimising off the reset counter thinking that the programmer didn't really mean it.

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the counter can power up to 0 upon configuration. is there a reason that won't work?

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Hi,

Can you please tell me how to initialize it to zero upon configuration?

Thanks,

Boris.

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Hi,

Can you please tell me how to initialize it to zero upon configuration?

Thanks,

Boris.

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signal count: integer range 0 to 31 := 0; -- or uncheck [don't care power up] in settings

clocked process...

...

if count < 31 then

count <= count + 1;

end if;

...

reset <= '1' when count < 31 else '0';

or something like that

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signal count: integer range 0 to 31 := 0; -- or uncheck [don't care power up] in settings

clocked process...

...

if count < 31 then

count <= count + 1;

end if;

...

reset <= '1' when count < 31 else '0';

or something like that

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1. I thought that initiating a signal with a logical value upon declaration has no meaning... Am I correct?

2. In settings, do you mean in Quartus?

Thanks,

Boris.

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1. I thought that initiating a signal with a logical value upon declaration has no meaning... Am I correct?

2. In settings, do you mean in Quartus?

Thanks,

Boris.

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Modern synthesis tools are more polite and respect initial value for power up.

Yes Quartus settings