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Altera_Forum's avatar
Altera_Forum
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13 years ago

Self reset to FPGA

Hi, I'm integrating an independent FPGA which doesn't have a master CPU associated with it. I need to reset the FPGA right after it enters user mode. Will using Init_done signal Anded with Co...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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1. I thought that initiating a signal with a logical value upon declaration has no meaning... Am I correct?

2. In settings, do you mean in Quartus?

Thanks,

Boris.

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Modern synthesis tools are more polite and respect initial value for power up.

Yes Quartus settings