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Altera_Forum's avatar
Altera_Forum
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12 years ago

Self reset to FPGA

Hi, I'm integrating an independent FPGA which doesn't have a master CPU associated with it. I need to reset the FPGA right after it enters user mode. Will using Init_done signal Anded with Co...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

--- Quote Start ---

Hi,

Can you please tell me how to initialize it to zero upon configuration?

Thanks,

Boris.

--- Quote End ---

signal count: integer range 0 to 31 := 0; -- or uncheck [don't care power up] in settings

clocked process...

...

if count < 31 then

count <= count + 1;

end if;

...

reset <= '1' when count < 31 else '0';

or something like that