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Altera_Forum's avatar
Altera_Forum
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13 years ago

Self reset to FPGA

Hi, I'm integrating an independent FPGA which doesn't have a master CPU associated with it. I need to reset the FPGA right after it enters user mode. Will using Init_done signal Anded with Co...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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I'm using the method in a number of production designs where the hardware guys didn't provide a hardware reset signal.

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Sorry to hear you have some hardware guys around you who are really hard and unhelpful.

I myself have used internal reset instead of external one and it worked most but not every time. We assumed if the design didn't start well then the customer will instinctively power up again or give it a shake.

The power up reset was even regular reset whenever certain errors flagged that will force the counter back to zero. This also prevented compiler from optimising off the reset counter thinking that the programmer didn't really mean it.