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Honored Contributor
Honored ContributorSelf reset to FPGA
Hi, I'm integrating an independent FPGA which doesn't have a master CPU associated with it. I need to reset the FPGA right after it enters user mode. Will using Init_done signal Anded with Co...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- signal count: integer range 0 to 31 := 0; -- or uncheck [don't care power up] in settings clocked process... ... if count < 31 then count <= count + 1; end if; ... reset <= '1' when count < 31 else '0'; or something like that --- Quote End --- 1. I thought that initiating a signal with a logical value upon declaration has no meaning... Am I correct? 2. In settings, do you mean in Quartus? Thanks, Boris.
