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Altera_Forum's avatar
Altera_Forum
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16 years ago

SDRAM on DE2-70

Hi all

I tried to use SDRAM in nios II but no result

In sopc I used PLL with 100 MHZ for system clock

and I used 100 MHZ with -3 ns for SDRAM controller.

In Nios II IDE i tried to use IOWR_16DIRECT, its OK

but when I want to read from the same address the result is FFFF

also I used __attribute__ ((section (".sdram")) no result

also I tried to use fopen fread ...... etc but give me undefiend reference for....

What shall I do???????????????

please give me the best way to store data that comes from UART to store them into SDRAM for Image processing.

NEED YOUR HELP.

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    115200 kbit/sec is far away from too high, 921600 kbit/sec with a normal pc uart is no problem IF you use hardware handshake RTS & CTS and FIFO's to enshure that the transmission is stalled when the data can't be processed in "realtime"

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    No I just want to how to transfer data from PC to SDRAM, I've used UART before but some data lossed I don't know may be for baud rate 112500 is high, also I've tried with fopen fread but with error.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    fine. so this was easily done.

    but your question now is application related and there so many diferent ways to do that and what you want to do. sorry can't give you some advice here
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Thanks alot.

    All things is going OK.:)

    Now I want to load Image from PC to SDRAM.

    Is there a way that I load this Image without convert it to numbers.

    Beacuse in NIOS II IDE i copied Image in the project folder when double click it opend in the IDE such as using of Paint in windows.

    If not, Could you aadvice me the best and fastet way to load data from PC, for example by using UART or fopen,fread......, or what?

    B.regards.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    lets assume pll's output c0 is your 100 MHz for nios cpu and other stuff and lets say pll output c1 is 100MHz with a phase shift -3ns.

    then you should connect c0 to nios and sdram controller ip, but c1 with the phase shift to the external sdram chips the sdram_clk pin

    so i guess your mistake is that you use the clock with the phase shift as the sdram controller ip clock.