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Honored Contributor
Honored ContributorSDRAM on DE2-70
Hi all I tried to use SDRAM in nios II but no result In sopc I used PLL with 100 MHZ for system clock and I used 100 MHZ with -3 ns for SDRAM controller. In Nios II IDE i tried to use IOWR_...
Altera_ForumHonored Contributor
Honored Contributorlets assume pll's output c0 is your 100 MHz for nios cpu and other stuff and lets say pll output c1 is 100MHz with a phase shift -3ns.
then you should connect c0 to nios and sdram controller ip, but c1 with the phase shift to the external sdram chips the sdram_clk pin so i guess your mistake is that you use the clock with the phase shift as the sdram controller ip clock.
