New ContributorMAX 10 devices feature selectable Schmitt Trigger on all inputs. The question is if the dedicated PLL input pin is affected by the Schmitt Trigger when it is enabled, or if the PLL input bypasses the Schmitt Trigger.
I don't see this specified in the documentation. Neither I see this in the IOE structure diagram.
Thanks,
New ContributorSorry to bump the topic. But after two weeks I would appreciate an answer.
Thanks,
Super ContributorNew ContributorI agree that it wouldn't make much sense that the Schmitt Trigger would be completely disabled if it drives a PLL. That wasn't exactly my question. My question was if the dedicated PLL input is connected to the Schmitt Trigger at all. Conceivable, the dedicated PLL input could always bypass the ST, even when the ST is still enabled for the normal (non PLL) I/O.
Regular ContributorHello,
Based on the User Guide, I believe they should be separated for the dedicated clock input pin.
New Contributor
@AqidAyman_Intel wrote:Hello,
Based on the User Guide, I believe they should be separated for the dedicated clock input pin.
Hi AqidAyman,
I'm not sure I understand exactly what you mean by "they". Note that the expression "dedicated PLL input", used in Altera documentation, is a bit misleading. It is not exactly dedicated in the sense that it can be only used for driving a PLL. It can also be used as a normal input, even at the same time that it is used as the PLL clock input.
Wouldn't be possible to get an authoritative answer to this?
Thanks,
Regular ContributorSchmit trigger should not affect the dedicated clock input pins unless the clock has some glitch.
May I know why do you have this concern?
Regards,
Aqid
New ContributorHi Aqid,
That's the whole point. But I am not concerned about the Schmitt Trigger producing any negative effects. It's actually the opposite. I am wondering if the PLL could perform better in noisy environments in comparison to other parts that don't have Schmitt Trigger.
But for some reason I still didn't receive an answer. If the dedicated PLL input can be connected to the Schmitt Trigger, or if the PLL input always bypasses the Schmitt Trigger, even when it's enabled for non PLL functionality. I don't understand why this hasn't been answered yet. I assume this is not any kind of confidential information. Or is it?
Thanks,
Super ContributorSuper ContributorHi,
ST is an IO-standard (e.g. 3.3-V Schmitt Trigger) assigned to the input pin. So if actually implemented, it applies to any function driven by the pad. Similarly, if you assign LVDS IO-standard to the pin, your PLL input becomes differential.
It's pointless to assume a path to PLL bypassing the input buffer. If at all, the ST function would be disabled by the fitter, but I can't believe that it's still consistenly flagged in Pin-Out file, Resource Porperty Editor, Fitter Report Resource Section.
Regards
Frank
Regular ContributorFrom the principle of Schmitt Trigger, you could see it mainly filter the glitch of input signal.
The PLL performance depends on the jitter of input clock mainly, so I don’t think the Schmitt trigger could optimize the PLL performance.
New ContributorHi Aqid,
I think you misunderstood me. I didn't say, or at least I didn't mean, that the Schmitt Trigger would improve the PLL performance. Not in that sense. But never mind. I think we are not going anywhere with this discussion and probably better just to close the topic.
Thanks,
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Super ContributorHi,
I had an occasion to measure properties of MAX10 clock input and found above expected behaviour. A configured Schmitt Trigger feature also works on PLL input. I could specfically see that a low slew rate clock signal as shown below caused loss of PLL lock with 3.3V LVCMOS IO standard but runs fine with 3.3V Schmitt Trigger input.
Regards
Frank
New ContributorVery useful test.
Thanks Frank,
