Forum Discussion
Hi Aqid,
That's the whole point. But I am not concerned about the Schmitt Trigger producing any negative effects. It's actually the opposite. I am wondering if the PLL could perform better in noisy environments in comparison to other parts that don't have Schmitt Trigger.
But for some reason I still didn't receive an answer. If the dedicated PLL input can be connected to the Schmitt Trigger, or if the PLL input always bypasses the Schmitt Trigger, even when it's enabled for non PLL functionality. I don't understand why this hasn't been answered yet. I assume this is not any kind of confidential information. Or is it?
Thanks,
I don't see an indication for a hidden feature that selectively disables ST input for PLLs but keeps erroneously the ST info in property editor. If you think though, it could be so, you can verify actual device behaviour by specific measurements.
- jAlter1 year ago
New Contributor
Hi FvM,
Thanks again for your reply, but I don't follow your reasoning. I'm not claiming there is any kind of hidden feature. And I'm certainly not saying that the Property Editor displays wrong information.
But again, how do you know if the Property Editor info applies to the PLL input? Please keep in mind that the PLL dedicated input pin is not used exclusively for the PLL. The term dedicated is a bit misleading here. The very same pin can also be used for regular (non PLL) I/O as well, even simultaneously with the PLL.
The Property Editor shows the Schmitt Trigger status only when you examine the I/O Pad resource. When you examine the PLL resource the Property Editor doesn't show any specific information about the clock input. At least this is true in the Quartus versions I checked. So, if you enable the ST, it is shown in the Property Editor pad resource, because it would still apply to the non PLL usage on that same pin. It is not wrong or erroneous info.
I hope I am explaining myself correctly, because otherwise I don't understand your point. You seem to be ignoring that the pin is not really exclusive for the PLL. Please let me know if the paragraph above makes some sense to you.
Now, it is possible that indeed, the ST applies to the PLL input as well. But it is also possible that it does not. It is possible that the PLL input comes from a node at the pad before the ST enable/disable mux. It might make some sense because the ST enable/disable mux probably adds some jitter. And the mux itself, obviouslly, cannot be disabled. Hence why I am asking.
Yes, I guess it is possible to make some measurements. But I don't think that's a very easy measurement to perform. And honestly, I expected that an Altera employee with authoritative knowledge would give a definitive answer.
Thanks,