Forum Discussion
FvM
Super Contributor
2 months agoHi,
I had an occasion to measure properties of MAX10 clock input and found above expected behaviour. A configured Schmitt Trigger feature also works on PLL input. I could specfically see that a low slew rate clock signal as shown below caused loss of PLL lock with 3.3V LVCMOS IO standard but runs fine with 3.3V Schmitt Trigger input.
Regards
Frank
- jAlter2 months ago
New Contributor
Very useful test.
Thanks Frank,