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Altera_Forum's avatar
Altera_Forum
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16 years ago

Safe clock division

Hi all,

I've been researching this for a while (because the Classic Timing Analyzer has failing paths) but here's my question:

What is the safest way to divide down a clock? Currently I'm using a few ripple counters (not very safe due to clock skew). I'm trying to divide a clock down by 16 (power of 2, so it shouldn't be that difficult) I can't use a PLL because the clock I need is too slow, so that's out of the question.

Any ideas? I haven't seen any clock managers (such as the DCM in Xilinx)

Thanks for all replies!

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    I haven't seen any clock managers (such as the DCM in Xilinx)

    --- Quote End ---

    Recent Altera FPGAs (e.g. Cyclone III) have PLL frequency ranges similar to Xilinx DCM.

    To implement a slower clock within a design, usually clock enables rather than divided clocks are the suitable means in most cases.

    The clock divider can e.g. generate a signal that is high for one of 16 system clock cycles, using a synchronous counter. It can act as enable condition in an edge sensitive process/always block.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Wouldn't those enables be made in a manner similar to a divided clock? Does the enable structure remove the clock skew that would be implemented in a ripple counter?

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    Does the enable structure remove the clock skew that would be implemented in a ripple counter?

    --- Quote End ---

    Yes, it's not clock gating. 

    process (clk)
begin
  if rising_edge(clk) then
    -- code executed every clock cycle
    if cnt = 15 then
      cnt <= (others => '0);
      clk_enable <= '1';
    else
      cnt <= cnt + 1;
      clk_enable <= '0';
    end if;
    if clk_enable = '1' then
      -- code executed at the divided rate
    end if;
  end if;
end process;
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I see. Thank you for your help.

    However, (worst case scenario) what can I do if an enable structure just won't work? And I have to make my own clock? Is there anything better than a ripple counter?
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    However, (worst case scenario) what can I do if an enable structure just won't work? And I have to make my own clock? Is there anything better than a ripple counter?

    --- Quote End ---

    A clock enable would always work (why it wouldn't?).

    If you still insist in using a divided clock for some reason, then a possible solution to hold violations is to not use the original clock for driving registers, use a buffered/registered clock instead. The idea is that both clocks, the divided and the one with the original frequency, would have similar delay-skew with respect to the original clock signal. And then the skew between them, would be smaller.

    Another possibility, usable only in some cases, is to use the opposite edge of the original clock to produce the division.