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Altera_Forum's avatar
Altera_Forum
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16 years ago

Safe clock division

Hi all, I've been researching this for a while (because the Classic Timing Analyzer has failing paths) but here's my question: What is the safest way to divide down a clock? Currently I...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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Does the enable structure remove the clock skew that would be implemented in a ripple counter?

--- Quote End ---

Yes, it's not clock gating. 

process (clk)
begin
  if rising_edge(clk) then
    -- code executed every clock cycle
    if cnt = 15 then
      cnt <= (others => '0);
      clk_enable <= '1';
    else
      cnt <= cnt + 1;
      clk_enable <= '0';
    end if;
    if clk_enable = '1' then
      -- code executed at the divided rate
    end if;
  end if;
end process;