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Honored Contributor
Honored ContributorSafe clock division
Hi all, I've been researching this for a while (because the Classic Timing Analyzer has failing paths) but here's my question: What is the safest way to divide down a clock? Currently I...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- However, (worst case scenario) what can I do if an enable structure just won't work? And I have to make my own clock? Is there anything better than a ripple counter? --- Quote End --- A clock enable would always work (why it wouldn't?). If you still insist in using a divided clock for some reason, then a possible solution to hold violations is to not use the original clock for driving registers, use a buffered/registered clock instead. The idea is that both clocks, the divided and the one with the original frequency, would have similar delay-skew with respect to the original clock signal. And then the skew between them, would be smaller. Another possibility, usable only in some cases, is to use the opposite edge of the original clock to produce the division.
