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Honored Contributor
Honored ContributorSafe clock division
Hi all, I've been researching this for a while (because the Classic Timing Analyzer has failing paths) but here's my question: What is the safest way to divide down a clock? Currently I...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I haven't seen any clock managers (such as the DCM in Xilinx) --- Quote End --- Recent Altera FPGAs (e.g. Cyclone III) have PLL frequency ranges similar to Xilinx DCM. To implement a slower clock within a design, usually clock enables rather than divided clocks are the suitable means in most cases. The clock divider can e.g. generate a signal that is high for one of 16 system clock cycles, using a synchronous counter. It can act as enable condition in an edge sensitive process/always block.
