Altera_Forum
Honored Contributor
12 years agoReporting path delays from quartus flow into timequest report
Hi,
I'm struggeling with the tcl syntax of quartus. I learned just today that every tool has it's own packages. I'm using Quartus 13 I want to run quartus, and after quartus has compiled the complete design I want a timing report of a certain pin to two certain registers. Just for clarification, I don't want to run timequest by hand, I want the report after running quartus. To give an example, I have an rx pin, and I want to know the path delay from this rx pin to flipflop output sig_x and also from sig_y. See drawing below. It should show 4 square blocks representing a design. How to constrain that? And how to constrain that this, only appears in the TimeQuest Timing Analysis phase? In other words, how to use the Timequest package so that Analysis and Synthesis, and Fitter, don't start complaining that they don't understand this syntax.
+---------------------------------------------------------+
|TOP |
rx --->| |
| +-----------------------------------------------+ |
| |framehandler | |
| | | |
| | | |
| | | |
| | +----------------------------------------+ | |
| | |header_register | | |
| | | | | |
| | | | | |
| | | +-----------------------------------+ | | |
| | | |module_c | | | |
| | | | | | | |
| | | | +---+ | | | |
| | | | | |->sig_x | | | |
| | | | |> | | | | |
| | | | +---+ | | | |
| | | | | | | |
| | | | | | | |
| | | | | | | |
| | | | +---+ | | | |
| | | | | |->sig_y | | | |
| | | | |> | | | | |
| | | | +---+ | | | |
| | | | | | | |
| | | +-----------------------------------+ | | |
| | | | | |
| | +----------------------------------------+ | |
| | | |
| +-----------------------------------------------+ |
| |
+---------------------------------------------------------+
Rgds, Kimberley