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Altera_Forum
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16 years ago

Remote Update Cyclone III from EPCS

I am able to load in an Application configuration from a specified address in the EPCS, but after a certain time the device reconfigures itself with the Factory configuration (at address 0).

I am not using a Nios processor. Reconfiguration is controlled by an external processor and a simple state machine in the FPGA.

It seems that the first time I trigger the device to reconfigure itself with the Application configuration (address 30000) it will immediately reconfigure itself with the Factory configuration. On subsequent times it will keep the Application configuration for about a minute before reconfiguring itself with the Factory configuration.

It seems like it has something to do with the watchdog timer, but I have not enabled it. I have not been successful yet in reading back the status from the Remote Update circuit so I can't tell what caused the reconfiguration. I connected a signal that has a short pulse every millisecond up to the reset_timer line but that made it such that the FPGA would revert back to Factory configuration immediately every time I triggered a reconfiguration with the Application configuration.

Any ideas on what to look for would be appreciated.

14 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Watchdog timer would have been my first guess as well. Another thing to check though is if there is a bug in your software (overrunning memory, invalid pointer) and you're accidentally writing to the remote_update core and performing a restart.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    One way to check is to get the processor running in application mode, then connect to the processor using the NIOS II debugger. Let the processor remain paused and see if the FPGA still gets reconfigured.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I don't have a Nios processor.

    I use some simple logic in the FPGA and an external processor.

    I know the external processor is not triggering the reconfiguration at random times because I am manually forcing the event by writing to a specific address. I never get an unexpected reconfiguration when running with the Factory image.

    Can you point me to any documentation that shows what the default state of the watchdog is? I am not enabling it, but it really seems like that is what is triggering the reconfiguration.

    Thanks.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I added logic to explicitly disable the WDT and it fixed the problem.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    David, or anyone - I am seeing the exact same behavior in my testing. I'm wondering what you did to disable the WDT.

    I have tried tieing reset_timer to a '1' in the VHDL with no success and have tried setting it to a '1' under software control after I see the RSU succeed but that does not work either.

    Any thoughts?

    Thanks

    Keivn.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I have written state machines for factory and application images -cyclone3-AS mode-EPCS16.

    Do I need ALTASMI mega function to connect serial device(I2C)?

    I read that there is no need of ALTASMI.But,how the data transfer takes place between I2C and EPCS?

    How do I build SOPC?Greatly appreciate if anyone can guide me!
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Thanks David - I coded up something similar to what you suggested and it is working well now. Funny thing is (I thought) we were doing the same steps in software before and it did not. But thanks again I appreciate your help.

    - Kevin.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Brunda - Yes, you need the ALTASMI core in your code. The pin mapping is transparent but you need it there to make the connection between your state machine and the ASMI (hard macro) block itself.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Thanks very much for your quick reply.

    Following on the same,the image update circuit has the controller logic & update logic.

    The controller logic reads the data from I2C and the update logic writes the image from the controller logic to EPCS.

    Its not fully clear to me how to use I2C with controller logic.

    The I2C that i'm using has both slave and master pins.

    Greatly appreciate your inputs.