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Altera_Forum
Honored Contributor
15 years agoDavid, or anyone - I am seeing the exact same behavior in my testing. I'm wondering what you did to disable the WDT.
I have tried tieing reset_timer to a '1' in the VHDL with no success and have tried setting it to a '1' under software control after I see the RSU succeed but that does not work either. Any thoughts? Thanks Keivn.