Altera_Forum
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Altera_ForumI would argue that timing analysis is a must. At a bare minimum, you need to make sure that you have no hold time failures. If you do not eliminate the timing violations, there is a risk that your design will not work as your lab conditions change or if you load your design on another FPGA. Everything may be working now, but beware...
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I should further add that I would never put a design in production that shows timing violations unless I have been able to analytically demonstrate that the violations can be waived. If that is the case, a timing exception, i.e., false path or multicycle path, should be implemented to mask the "bogus" violation.
- Altera_Forum
I agree to Brett on this. I would say that you atleast look at the timing violations and make sure that those are not going to affect your design. I guess that in this case most of the violation (if not false) would be hold violations as most of the FPGAs would be able to meet the 2 Mhz timing without the timing constraints been given. But hold violation can be as dangerous as any other timing violations, so beware.
- Altera_Forum--- Quote Start --- hi, 1.is timing analysis compulsory for low speed fpga design(<2MHz). 2.my design is working properly, but in compilation report it is showing that timing requirements are not met. in such case timing analysis is required? with regards --- Quote End --- Hi, can you post some of your timing violations here ? Which timing analyzer do you use ? Kind regards GPK
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hi
1.if i have not given any sdc file it showing some unconstrained paths in timequest timing analyzer ,what is the meaning of this. 2.in critical warning it showing "timing requirements are not met" 3. what is the meaning of critical warning found minimum pulse width or period violations. - Altera_Forum--- Quote Start --- hi 1.if i have not given any sdc file it showing some unconstrained paths in timequest timing analyzer ,what is the meaning of this. 2.in critical warning it showing "timing requirements are not met" 3. what is the meaning of critical warning found minimum pulse width or period violations. --- Quote End --- Hi, 1. Do you have an <>.sdc file or is your design fully unconstraint ? Unconstrained paths will be not consider in the timing analysis. 2. Means that you have timing violations in your design 3. This violation indicates that you have pulses in your design, which are too short. This could cause problems with e.g. Registers. Can you post your SDC file ? Kind regards GPK
- Altera_Forum
hi
i am not using any .sdc file. if i proceed with critical warnings ,is there any problem? can u give any basic idea for ,how to do timing analysis regards - Altera_Forum--- Quote Start --- hi i am not using any .sdc file. if i proceed with critical warnings ,is there any problem? can u give any basic idea for ,how to do timing analysis regards --- Quote End --- Hi, which FPGA and which timing analyzer did you use ? Kind regards GPK
