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Honored Contributor
Honored Contributorreg timing analysis
hi, 1.is timing analysis compulsory for low speed fpga design(<2MHz). 2.my design is working properly, but in compilation report it is showing that timing requirements are not met. in such cas...
Altera_ForumHonored Contributor
Honored ContributorI should further add that I would never put a design in production that shows timing violations unless I have been able to analytically demonstrate that the violations can be waived. If that is the case, a timing exception, i.e., false path or multicycle path, should be implemented to mask the "bogus" violation.
