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Honored Contributor
Honored Contributorreg timing analysis
hi, 1.is timing analysis compulsory for low speed fpga design(<2MHz). 2.my design is working properly, but in compilation report it is showing that timing requirements are not met. in such cas...
Altera_ForumHonored Contributor
Honored Contributorhi
i am not using any .sdc file. if i proceed with critical warnings ,is there any problem? can u give any basic idea for ,how to do timing analysis regards
