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Honored Contributor
Honored Contributorreg timing analysis
hi, 1.is timing analysis compulsory for low speed fpga design(<2MHz). 2.my design is working properly, but in compilation report it is showing that timing requirements are not met. in such cas...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- hi 1.if i have not given any sdc file it showing some unconstrained paths in timequest timing analyzer ,what is the meaning of this. 2.in critical warning it showing "timing requirements are not met" 3. what is the meaning of critical warning found minimum pulse width or period violations. --- Quote End --- Hi, 1. Do you have an <>.sdc file or is your design fully unconstraint ? Unconstrained paths will be not consider in the timing analysis. 2. Means that you have timing violations in your design 3. This violation indicates that you have pulses in your design, which are too short. This could cause problems with e.g. Registers. Can you post your SDC file ? Kind regards GPK
