Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorreg timing analysis
hi, 1.is timing analysis compulsory for low speed fpga design(<2MHz). 2.my design is working properly, but in compilation report it is showing that timing requirements are not met. in such cas...
Altera_ForumHonored Contributor
Honored ContributorI agree to Brett on this. I would say that you atleast look at the timing violations and make sure that those are not going to affect your design. I guess that in this case most of the violation (if not false) would be hold violations as most of the FPGAs would be able to meet the 2 Mhz timing without the timing constraints been given. But hold violation can be as dangerous as any other timing violations, so beware.
