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Honored Contributor
Honored Contributorreg timing analysis
hi, 1.is timing analysis compulsory for low speed fpga design(<2MHz). 2.my design is working properly, but in compilation report it is showing that timing requirements are not met. in such cas...
Altera_ForumHonored Contributor
Honored ContributorI would argue that timing analysis is a must. At a bare minimum, you need to make sure that you have no hold time failures. If you do not eliminate the timing violations, there is a risk that your design will not work as your lab conditions change or if you load your design on another FPGA. Everything may be working now, but beware...
