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Altera_Forum
Honored Contributor
Honored ContributorRealization MFM de/en-Coder via MAXII
Hello @ All,
I'm new here and I hope that someone can help me concerning matter above. Background: I work almost honorary in my spare time for the computer museum in Munich and my goal is to transfer vintage Computer/Storage to new technology like FPGA and ARM-7 MCU. For more details, I want to refer to my homepage . Right now, I have a big hurdle:confused:: Realizing mfm encoders and decodersin the FPGA/MAXII. I haven't found the right references until now. I am working here with a magnetic device with all the preemphasis stuff and phase shifting around and this is really a piece of complicated hardware ( for me ). To rebuild this piece of hardware in FPGA related to the RLV-12 engineering drawings, it is still not clear to me how to realize the 5nsec delay logic in the FPGA and furthermore I don't know the ROM code for the phase-moving logic to get it in the FPGA. It is also not clear yet whether I need this all. My question:- Has someone references how to get implemented a MFM de/en-Coder logic in FPGA?
- How can I realize a 9x 50nsec delay in FPGA?
- How can I implement a ROM , 32x8bit in FPGA?
21 Replies
Altera_ForumNow, its working fine, Thanks !
- Altera_Forum
oooops .. i shouldn't code something while having lunch ...
please replace the file, it works now. - Altera_Forum
many many thanks for your efforts!
That's brilliant ! Conclusion for me: I have to learn VHDL... Regards, Reinhard - Altera_Forum
have a look into the zip, it contains a verilog source and the schematic symbol for it.
place both files into your project directory now you will find a new symbol you can add to your schematic entry. add the 50MHz clock input and you should get the pulse at the output - Altera_Forum
hmmm 16kHz is 50MHz div by 833.333 and i guess you need it accurate ...
give me a minute or two ... - Altera_Forum
Since I am not so good in VHDL , I would prefere a wiring diagram if possible. For me it is not clear how a 16kHz clock can generated based on the only 50 MHz clock available on MAXII.
- Altera_Forum
62,5uSec = 16kHz clock
the period is 10 times the clock so you need a clock or an clock enable that is 1 every 62,5uSec verilog HDL reg [3:0] counter; always @ ( posedge my16khzclock ) if ( counter === 4'd0 ) counter == 4'd9; // this reload the counter else counter <= counter - d'd1; now you have a counter that counts down from 9 to 0 and then reloads to 9 again. that is your period of 625uSec, assuming you have a correct clock. now the output signal, that could be a register or combinatorical wire mypulse; assign mypulse = !counter; or reg mypulse; always @ ( posedge my16khzclock ) if ( counter === 4'd0 ) mypulse <= 1'b1; else mypulse <= 1'b0; now mypulse should be 1 for a single my16khzclock cycle every 10 cycles. - Altera_Forum
Hello,
many thanks for the upgrade infos. The notes concerning double frequency clock were not very helpful to me, but I know that the problem lies in my person because I don't understand VHDL very well and the MAXII was not the right decision for my project. Anyway, I was able to design a double frequency circuit based on my "old" digital-logic-knowledge as you can see in the appendix. It's basically a simplified PLL without VCO , but works fine and may be helpful for other people? I still have a small problem now: Generate a sector pulse like here: ____-----------_______________________________-----------_____ ----|>62.5 us<| ----|> ------------------- 625 us ---------------->| Sight from my "old" person , I would be able to fix this problem with 2 external NE555 timer chip ( within 2 hour soldering ) but this is not the manner like it should be. Has somebody an idea to realize this timing ? Many thanks and best regards, Reinhard - Altera_Forum
A double frequency clock can be generated by a delay (either RC circuit or a logic cell chain) and a XOR gate.
Some references for logic cell delay, also discussing the limitations. http://www.alteraforum.com/forum/showthread.php?t=2418 http://www.alteraforum.com/forum/showthread.php?t=3068 - Altera_Forum
Hello again with one open key-issue:
For the MFM Decoder/Encoder, I need a 8.2MHz clock. The half frequency 4.1MHz is available via I/O connecter distributed from the controller. Basically, I have to double phase-synchronize the 4.1MHz clock. The answer is a PLL, but the altpll megafunction is not supported by the selected device family MAXII. Realy bad for me. Is there a alternative suggestion available ?
