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MaxII is a CPLD not a FPGA
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By it's technology, MAX II is a simple FPGA with built-in configuration flash. The logic elements are SRAM based in contrast to a EEPROM based CPLD cells. You'll also notice, that MAX II uses the Quartus FPGA related tools, while MAX 3000 and 700 are using a different compiler/fitter.
But anyway, it's capable of performing at 200 MHz clock frequency. As a disadvantage, it hasn't any PLL or clock multiplier, so you must supply a 200 MHz clock input (or at least 100 MHz when using both edges). A full featered FPGA with PLL could use a convenient 10 or 20 MHz clock.
MAX II has no internal RAM or ROM, but 32x8 can be made in MAX II logic cells.
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