Realization MFM de/en-Coder via MAXII

Reinhard,

just to give you an example how the conversion from your schematic to verilog could look like here are some few code snippets ...

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Lets starts with the toggle DFF from the lower left corner

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reg E128;

always @ ( posedge Clk_8_2Mhz )

E128 <= ~E128;

wire RLVA_SYS_1H;

wire RLVA_SYS_0H;

assign RLVA_SYS_1H = E128;

assign RLVA_SYS_0H = ~E128;

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now the shift register E117

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// The shift register from Page 23 at the bottom;

reg [4:0] E117;

always @ ( posedge Clk_8_2Mhz or negedge RLV9_INIT_0L )

if ( !RLV9_INIT_0L )

E117 <= 4'd0;

else

E117[4:0] <= { E117[3:0] , RLV_MUX_DATA_H };

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now the ROM E120 82S123

implemented as priority encoded wires .... well at 8.2MHz i don't worry about timing here

this could also be implemented as a memory and initialised from a file

but strictly implemented from original schematic without 1 clock delay a register would give

it is done this way ... without propper values

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wire [4:0] PROM_E120;

assign PROM_E120 = ( E117 === 5'H00 ) ? 5'b00000 :

( E117 === 5'H01 ) ? 5'b00000 :

( E117 === 5'H02 ) ? 5'b00000 :

( E117 === 5'H03 ) ? 5'b00000 :

( E117 === 5'H04 ) ? 5'b00000 :

( E117 === 5'H05 ) ? 5'b00000 :

( E117 === 5'H06 ) ? 5'b00000 :

( E117 === 5'H07 ) ? 5'b00000 :

( E117 === 5'H08 ) ? 5'b00000 :

( E117 === 5'H09 ) ? 5'b00000 :

( E117 === 5'H0A ) ? 5'b00000 :

( E117 === 5'H0B ) ? 5'b00000 :

( E117 === 5'H0C ) ? 5'b00000 :

( E117 === 5'H0D ) ? 5'b00000 :

( E117 === 5'H0E ) ? 5'b00000 :

( E117 === 5'H0F ) ? 5'b00000 :

( E117 === 5'H10 ) ? 5'b00000 :

( E117 === 5'H11 ) ? 5'b00000 :

( E117 === 5'H12 ) ? 5'b00000 :

( E117 === 5'H13 ) ? 5'b00000 :

( E117 === 5'H14 ) ? 5'b00000 :

( E117 === 5'H15 ) ? 5'b00000 :

( E117 === 5'H16 ) ? 5'b00000 :

( E117 === 5'H17 ) ? 5'b00000 :

( E117 === 5'H18 ) ? 5'b00000 :

( E117 === 5'H19 ) ? 5'b00000 :

( E117 === 5'H1A ) ? 5'b00000 :

( E117 === 5'H1B ) ? 5'b00000 :

( E117 === 5'H1C ) ? 5'b00000 :

( E117 === 5'H1D ) ? 5'b00000 :

( E117 === 5'H1E ) ? 5'b00000 :

5'b00000 ;

// now we assign the output bits of the PROM the names as used by the schematics

wire RLVA_B0_H;

wire RLVA_B1_H;

wire RLVA_B2_H;

wire RLVA_B3_H;

wire RLVA_B4_H;

assign RLVA_B0_H = PROM_E120[0];

assign RLVA_B1_H = PROM_E120[1];

assign RLVA_B2_H = PROM_E120[2];

assign RLVA_B3_H = PROM_E120[3];

assign RLVA_B4_H = PROM_E120[4];

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last but not least the counter at the lower right

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reg [3:0] E125;

always @ ( posedge Clk_8_2Mhz or negedge RLV9_INIT_0L )

if ( !RLV9_INIT_0L )

// async nCLR

E125 <= 4'd0;

else

if ( RLVA_SYS_0H ^ RLVA_R0_H )

// nLOAD

E125 <= { RLVA_B4_H , RLVA_B3_H , RLVA_B2_H , RLVA_B0_H };

else

// normal count operation

E125 <= E125 + 4'd1;

// again assign output bits the name of used by schematics

wire RLVA_R0_H;

wire RLVA_R1_H;

wire RLVA_R2_H;

wire RLVA_R3_H;

assign RLVA_R0_H = E125[0];

assign RLVA_R1_H = E125[1];

assign RLVA_R2_H = E125[2];

assign RLVA_R3_H = E125[3];

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