Realization MFM de/en-Coder via MAXII

Well if MaxII runs @ 200MHz what i haven't tried yet there are some other points to consider. if the design runs with 200MHz and 8.2MHz then some kind of clock crossing must be taken into account. but it is also possible to run the design at 200MHz and have some kind of clock enable that has 1 200MHz clock pulse every 8.2MHz (too keep the design fully synchronous)

another question what needs to be implemented inside the fpga except page 23 ?

you talked about 10240 byte fifo that could be implemented with 20 M4K memory blocks cyclone II fpga offers.

as you are new to the quartus world and fpga as well, did you had a look at the schematic entry possabilities quartus offers ? if you look at your page 23 there are some 7474 at the bottom, you can also draw such a logic with quartus. this tool is capable to handle hdl and schematic entry in a mixed combination.

i had converted a couple of old schematics (like some arcade classics) into pure verilog designs and sometimes the asyncron design to fully synchrnous conversion was a heavy task, but what worries me in your design are the two signal delay lines one 50ns with a tap each 5ns and the other one i have seen with 100ns delay and a tap each 10ns. they can be seen as shift registers with a high clock rate.

so what amount of logic do you want to transfer to a fpga and what kind of help could be give to you ?