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lipingx's avatar
lipingx
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

qustion for ddr2 driver ALTMEMPHY

hello,

I am not sure how to handle below warning.

Whereever the clock pin is put, there is still such warning.

I tried to put fpga clock input pin for any bank .

Critical Warning (332049): Ignored create_generated_clock at demo.out.sdc(50): Argument <targets> is an empty collection
Info (332050): create_generated_clock -name {pll_sys_clk} -source [get_ports {osc_clk}] -multiply_by 1 [get_pins {pll_clock_0|altpll_component|auto_generated|pll1|clk[0]}]
Critical Warning: PLL clock ddr_driver_0|ddr_driver_controller_phy_inst|ddr_driver_phy_inst|ddr_driver_phy_alt_mem_phy_inst|clk|pll|altpll_component|auto_generated|pll1|clk[1] driven through clock routing. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated clock pin on the same side.
Critical Warning: PLL clock ddr_driver_0|ddr_driver_controller_phy_inst|ddr_driver_phy_inst|ddr_driver_phy_alt_mem_phy_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3] driven through clock routing. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated clock pin on the same side.
Critical Warning: PLL clock ddr_driver_0|ddr_driver_controller_phy_inst|ddr_driver_phy_inst|ddr_driver_phy_alt_mem_phy_inst|clk|pll|altpll_component|auto_generated|pll1|clk[1] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.
Critical Warning: PLL clock ddr_driver_0|ddr_driver_controller_phy_inst|ddr_driver_phy_inst|ddr_driver_phy_alt_mem_phy_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.
Critical Warning: PLL clock ddr_driver_0|ddr_driver_controller_phy_inst|ddr_driver_phy_inst|ddr_driver_phy_alt_mem_phy_inst|clk|pll|altpll_component|auto_generated|pll1|clk[1] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.
Critical Warning: PLL clock ddr_driver_0|ddr_driver_controller_phy_inst|ddr_driver_phy_inst|ddr_driver_phy_alt_mem_phy_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.
Critical Warning: PLL clock ddr_driver_0|ddr_driver_controller_phy_inst|ddr_driver_phy_inst|ddr_driver_phy_alt_mem_phy_inst|clk|pll|altpll_component|auto_generated|pll1|clk[1] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.
Critical Warning: PLL clock ddr_driver_0|ddr_driver_controller_phy_inst|ddr_driver_phy_inst|ddr_driver_phy_alt_mem_phy_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.
Critical Warning: PLL clock ddr_driver_0|ddr_driver_controller_phy_inst|ddr_driver_phy_inst|ddr_driver_phy_alt_mem_phy_inst|clk|pll|altpll_component|auto_generated|pll1|clk[1] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.
Critical Warning: PLL clock ddr_driver_0|ddr_driver_controller_phy_inst|ddr_driver_phy_inst|ddr_driver_phy_alt_mem_phy_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.
Critical Warning: PLL clock ddr_driver_0|ddr_driver_controller_phy_inst|ddr_driver_phy_inst|ddr_driver_phy_alt_mem_phy_inst|clk|pll|altpll_component|auto_generated|pll1|clk[1] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.
Critical Warning: PLL clock ddr_driver_0|ddr_driver_controller_phy_inst|ddr_driver_phy_inst|ddr_driver_phy_alt_mem_phy_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.
Critical Warning (332049): Ignored create_generated_clock at demo.out.sdc(50): Argument <targets> is an empty collection
Info (332050): create_generated_clock -name {pll_sys_clk} -source [get_ports {osc_clk}] -multiply_by 1 [get_pins {pll_clock_0|altpll_component|auto_generated|pll1|clk[0]}]
Critical Warning: PLL clock ddr_driver_0|ddr_driver_controller_phy_inst|ddr_driver_phy_inst|ddr_driver_phy_alt_mem_phy_inst|clk|pll|altpll_component|auto_generated|pll1|clk[1] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.
Critical Warning: PLL clock ddr_driver_0|ddr_driver_controller_phy_inst|ddr_driver_phy_inst|ddr_driver_phy_alt_mem_phy_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.
Critical Warning: Warning (307078): ALTMEMPHY PLL, ddr_driver:ddr_driver_0|ddr_driver_controller_phy:ddr_driver_controller_phy_inst|ddr_driver_phy:ddr_driver_phy_inst|ddr_driver_phy_alt_mem_phy:ddr_driver_phy_alt_mem_phy_inst|ddr_driver_phy_alt_mem_phy_clk_reset:clk|ddr_driver_phy_alt_mem_phy_pll:pll|altpll:altpll_component|altpll_d8k3:auto_generated|clk[1], when fed by another PLL, must have the bandwidth mode set to High instead of Medium
Critical Warning: Warning (307078): ALTMEMPHY PLL, ddr_driver:ddr_driver_0|ddr_driver_controller_phy:ddr_driver_controller_phy_inst|ddr_driver_phy:ddr_driver_phy_inst|ddr_driver_phy_alt_mem_phy:ddr_driver_phy_alt_mem_phy_inst|ddr_driver_phy_alt_mem_phy_clk_reset:clk|ddr_driver_phy_alt_mem_phy_pll:pll|altpll:altpll_component|altpll_d8k3:auto_generated|clk[2], when fed by another PLL, must have the bandwidth mode set to High instead of Medium
Critical Warning: Read Capture and Write timing analyses may not be valid due to violated timing model assumptions
Critical Warning: Read Capture and Write timing analyses may not be valid due to violated timing model assumptions
Critical Warning: See violated timing model assumptions in previous timing analysis above
Critical Warning: Read Capture and Write timing analyses may not be valid due to violated timing model assumptions

Configuration

6 Replies

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi,


    The Quartus will ignore the constraint due to duplicate or not used sources.

    Try to check if there any clock constraint has been made to DDR interface.

    The DDR interface might generate it's own SDC file to constraint it's clock source.


    Regards,

    Adzim


    • lipingx's avatar
      lipingx
      Icon for Occasional Contributor rankOccasional Contributor
      2 years ago

      current clock solution, please help to check if such kind of clock for ddr pll_ref_clk has any problem or not?

      -> external oscillator 25MHz -> FPGA PLL -> C0 (25MHz for overall fpga system) + C1(75MHz for DDR pll_ref_clk )

      I also tried use external oscillator for connect to DDR pll_ref_clk directly.

      Then everything goes fine, no warning. Please let me know what's reason.

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    This is expected since the DDR has it's own PLL clock tree.

    The clock source should directly connect to the PLL reference clock.



  • lipingx's avatar
    lipingx
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    But I don't understand why there is problem using the clock output from another PLL.

    If we can share oscillator with DDR and other FPGA modules, it's cost effective.

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hello,


    It's about the timing closure concern.

    If you have good timing margin, then you can ignore for warning messages.

    If you have timing violation, then you have to feed the reference clock from a clock source.


    Regards,

    Adzim