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lipingx's avatar
lipingx
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

qustion for ddr2 driver ALTMEMPHY

hello, I am not sure how to handle below warning. Whereever the clock pin is put, there is still such warning. I tried to put fpga clock input pin for any bank . Critical Warning (332049): Ignore...
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AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi,


The Quartus will ignore the constraint due to duplicate or not used sources.

Try to check if there any clock constraint has been made to DDR interface.

The DDR interface might generate it's own SDC file to constraint it's clock source.


Regards,

Adzim


  • lipingx's avatar
    lipingx
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    I don't see scenario in my case.

    You can see below attached code.

  • lipingx's avatar
    lipingx
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    current clock solution, please help to check if such kind of clock for ddr pll_ref_clk has any problem or not?

    -> external oscillator 25MHz -> FPGA PLL -> C0 (25MHz for overall fpga system) + C1(75MHz for DDR pll_ref_clk )

    I also tried use external oscillator for connect to DDR pll_ref_clk directly.

    Then everything goes fine, no warning. Please let me know what's reason.