Question about normal differential I/O input ports pairs to Cyclone 10 GX interconnection

Hello FvM,

Thanks for you reply.

Our hardware design as following images. The exteranl CML pair signal (CBA_Trigger pair) is connected to C10GX's LVDS pair input I/O after resistance&capacitance termination (Trigger pair). According to you reply, this can't be supported for Cyclone 10 GX Serdes I/O?

If this is the case, we have to use one CML to LVDS converter chip to translate the CML signal to LVDS signal, then connect the converted signal to Cyclone 10GX Serdes I/O. Am i right?

Hello AqidAyman,

Are there any materials about how to connect CML pairs to FPGA lvds pairs?

Hello AqidAyman,

Thanks for you patience on this question.

I am asking the structure about interconnection between CML and LVDS. CML is dirver, and LVDS is receiver. In our case, the receiver is Cyclone 10 GX device. We use its LVDS I/O pairs as the receiver.

There are CML drivers outside of Cyclone 10 GX FPGA. These drivers need to be connected to FPGA. We connect them directly refer following description:

Intel FPGA has many LVDS receivers, so we think the external CML drivers can be fed into FPGA directly according to above image indication. BYW, there are two modes, AC coupling and DC coupling. Our hardware can implement these two modes.

So my question is that can C10GX devices LVDS receivers be used as above image's LVDS receivers? I just want to confirm with Intel engineer guys about this.

Thanks again.