Forum Discussion
MinzhiWang
Occasional Contributor
Occasional ContributorQuestion about normal differential I/O input ports pairs to Cyclone 10 GX interconnection
Hello guys, We are using 10CX220YF780E5G devices in our application. This FPGA mainly receive ADC output data by using LVDS differential pairs interface. I can find many posts here to discuss about ...
AqidAyman_Altera
Regular Contributor
Regular ContributorHello,
I am not quite sure if we have specific documentation that talks about the CML to LVDS hardware interconnecting.
However, I found a documentation that mention the CML I/O standard assignment, but this is related to Stratix 10 transceiver L and H-tile.
