Question about normal differential I/O input ports pairs to Cyclone 10 GX interconnection

Hello,

I am not quite sure if we have specific documentation that talks about the CML to LVDS hardware interconnecting.

However, I found a documentation that mention the CML I/O standard assignment, but this is related to Stratix 10 transceiver L and H-tile.

https://www.intel.com/content/www/us/en/docs/programmable/683621/current/reference-clock-i-o-standard.html