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MinzhiWang's avatar
MinzhiWang
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1 year ago

Question about normal differential I/O input ports pairs to Cyclone 10 GX interconnection

Hello guys, We are using 10CX220YF780E5G devices in our application. This FPGA mainly receive ADC output data by using LVDS differential pairs interface. I can find many posts here to discuss about ...
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FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
1 year ago
1. LVDS inputs are supporting Vicm downto 0V for speed upto 700 MBPS. Thus CML pair with resistive termination can directly drive LVDS input.
2. LVDS input can drive FPGA logic without restrictions. In contrast, Cyclone GX SERDES IO can only connect to LVDS IO standard.
MinzhiWang's avatar
MinzhiWang
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Hello FvM,

Thanks for you reply.

Our hardware design as following images. The exteranl CML pair signal (CBA_Trigger pair) is connected to C10GX's LVDS pair input I/O after resistance&capacitance termination (Trigger pair). According to you reply, this can't be supported for Cyclone 10 GX Serdes I/O?

If this is the case, we have to use one CML to LVDS converter chip to translate the CML signal to LVDS signal, then connect the converted signal to Cyclone 10GX Serdes I/O. Am i right?